WV3DG7266V-D1 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 1 preliminary* 512mb C 2x32mx72 sdram, unbuffered, w/pll features pc100 and pc133 burst mode operation auto and self refresh capability lvttl compatible inputs and outputs serial presence detect with eeprom fully synchronous: all signals are registered on the positive edge of the system clock programmable burst lengths: 1, 2, 4, 8 or full page 3.3v 0.3v power supply dual rank 144 pin so-dimm jedec ? pcb: 31.75mm (1.25) description the wv3dg7266v is a 2x32mx72 synchronous dram module which consists of nine stacked 64mx8 with 4 banks sdram components in tsop ii package, and one 2kb eeprom for serial presence detect which are mounted on a 144 pin so-dimm multilayer fr4 substrate. * this product is under development, is not quali? ed or characterized and is subject to change without notice. note: consult factory for availability of: ? rohs compliant products ? vendor source control options ? industrial temperature option pin names a0 C a12 address input (multiplexed) ba0-1 select bank dq0-63 data input/output clk0, clk1 clock input cb0-7 check bit (data-in/data-out) cke0 clock enable input cs0#, cs1# chip select input ras# row address strobe cas# column address strobe we# #write enable dqm0-7 dqm v cc power supply (3.3v) v ss ground sda serial data i/o scl serial clock dnu do not use nc no connect * these pins are not used in this module ** these pins should be nc in the system which does not support spd. pin configurations (front side/back side) pinout pin front pin back pin front pin back pin front pin back 1v ss 2v ss 49 dq13 50 dq45 97 dq22 98 dq54 3 dq0 4 dq32 51 dq14 52 dq46 99 dq23 100 dq55 5 dq1 6 dq33 53 dq15 54 dq47 101 v cc 102 v cc 7 dq2 8 dq34 55 v ss 56 v ss 103 a6 104 a7 9 dq3 10 dq35 57 cb0 58 cb4 105 a8 106 ba0 11 v cc 12 v cc 59 cb1 60 cb5 107 v ss 108 v ss 13 dq4 14 dq36 61 clk0 62 cke0 109 a9 110 ba1 15 dq5 16 dq37 63 v cc 64 v cc 111 a10 112 a11 17 dq6 18 dq38 65 ras# 66 cas# 113 v cc 114 v cc 19 dq7 20 dq39 67 we# 68 cke1 115 dqm2 116 dqm6 21 v ss 22 v ss 69 cs0# 70 a12 117 dqm3 118 dqm7 23 dqm0 24 dqm4 71 cs1#* 72 nc 119 v ss 120 v ss 25 dqm1 26 dqm5 73 nc 74 clk1 121 dq24 122 dq56 27 v cc 28 v cc 75 v ss 76 v ss 123 dq25 124 dq57 29 a0 30 a3 77 cb2 78 cb6 125 dq26 126 dq58 31 a1 32 a4 79 cb3 80 cb7 127 dq27 128 dq59 33 a2 34 a5 81 v cc 82 v cc 129 v cc 130 v cc 35 v ss 36 v ss 83 dq16 84 dq48 131 dq28 132 dq60 37 dq8 38 dq40 85 dq17 86 dq49 133 dq29 134 dq61 39 dq9 40 dq41 87 dq18 88 dq50 135 dq30 136 dq62 41 dq10 42 dq42 89 dq19 90 dq51 137 dq31 138 dq63 43 dq11 44 dq43 91 v ss 92 v ss 139 v ss 140 v ss 45 v cc 46 v cc 93 dq20 94 dq52 141 sda 142 scl 47 dq12 48 dq44 95 dq21 96 dq53 143 v cc 144 v cc
WV3DG7266V-D1 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 1 preliminary functional block diagram cs1# cs0# cas# ras# cke0 cke0: sdram cas#: sdram ras#: sdram a0-a12: sdram a0-a12 ba0-ba1 ba0-ba1: sdram we# we#: sdram cs0# cs0#: sdram cs1# cs1#: sdram v ss v cc sdram sdram two 0.1uf capacitors per each sdram serial pd sda scl a2 a1 a0 10 ? clk0 pll clock driver ck0 10pf 12pf clk1 10pf 10 ? dqn every dqpin of sdram 10 ? dqm0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqm4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cs# dqm cs# dqm cs# dqm cs# dqm dqm1 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqm5 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cs# dqm cs# dqm cs# dqm cs# dqm cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqm6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cs# dqm cs# dqm cs# dqm cs# dqm dqm2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqm7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cs# dqm cs# dqm dqm3 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cs# dqm cs# dqm cs# dqm cs# dqm
WV3DG7266V-D1 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 1 preliminary absolute maximum ratings parameter symbol value units voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v cc supply relative to v ss v cc , v ccq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 18 w short circuit current i os 50 ma note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. recommended dc operating conditions voltage referenced to: v ss = 0v, 0c t a +70c parameter symbol min typ max unit note supply voltage v cc 3.0 3.3 3.6 v input high voltage v ih 2.0 3.0 v ccq +0.3 v 1 input low voltage v il -0.3 0.8 v 2 output high voltage v oh 2.4 v i oh = -2ma output low voltage v ol 0.4vi ol = -2ma input leakage current i li -10 10 a 3 notes: 1. v ih (max)= 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min)= -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ccq input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. capacitance t a = 25c, f = 1mhz, v cc = 3.3v, v ref = 1.4v 200mv parameter symbol max unit input capacitance (a0-a12) c in1 95 pf input capacitance (ras#,cas#,we#) c in2 95 pf input capacitance (cke0) c in3 95 pf input capacitance (clk0) c in4 18 pf input capacitance (cs0#, cs1#) c in5 50 pf input capacitance (dqm0-dqm7) c in6 10 pf input capacitance (ba0-ba1) c in7 95 pf data input/output capacitance (dq0-dq63) c out 16 pf data input/output capacitance (cb0-7) c out1 16 pf
WV3DG7266V-D1 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 1 preliminary operating current characteristics (v cc = 3.3v, t a = 0c +70c) parameter symbol conditions value units note 77510 operating current (one bank active) i cc1 burst length = 1 t rc t rc (min) i o = 0ma 1170 1080 1080 ma 1 precharge standby current in power-down mode i cc2p cke v il (max), t cc = 10ns 36 ma 3 i cc2ps cke & clk v il (max), t cc = 36 precharge standby current in non power-down mode icc 2n cke v ih (min), cs# v ih (min), tcc =10ns input signals are charged one time during 20ns 360 ma 3 i cc2ns cke v ih (min), clk v il (max), t cc = input signals are stable 180 active standby current in power-down mode i cc3p cke v il (max), t cc = 10ns 108 ma 3 i cc3ps cke & clk v il (max), t cc = 108 active standby current in non-power down mode i cc3n cke v ih (min), cs# v ih (min), tcc = 10ns input signals are changed one time during 20ns 540 ma 3 i cc3ns cke v ih (min), clk v il (max), tcc = input signals are stable 450 ma 3 operating current (burst mode) i cc4 io = ma page burst 4 banks activated t ccd = 2clk 1260 1260 1170 ma 1 refresh current i cc5 t rc t rc (min) 2250 2070 1980 ma 2 self refresh current i cc6 cke 0.2v 54 ma 3 notes: 1. measured with outputs open. 2. refresh period is 64ms. 3. measured with 1 pll & 3 drive ics.
WV3DG7266V-D1 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 1 preliminary operating ac parameter parameter symbol version unit note 77510 row active to row active delay t rrd(min) 15 15 20 ns 1 ras# to cas# delay t rcd(min) 15 20 20 ns 1 row precharge time t rp(min) 15 20 20 ns 1 row active time t ras(min) 45 45 50 ns 1 t ras(max) 100 us row cycle time t rc(min) 60 65 70 ns 1 last data in to row precharge t rdl(min) 2 clk 2 last data in to active delay t dal(min) 2 clk + trp last data in to new col. address delay t cdl(min) 1 clk 2 last data in to burst stop t bdl(min) 1 clk 2 col. address to col. address delay t ccd(min) 1 clk 3 number of valid output data cas latency=3 2 ea 4 cas latency=2 1 notes: 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then roundi ng off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. ac operating test conditions v cc = 3.3v, 0c - 70c parameter value unit ac input levels (v ih /v il ) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall time t r /t f = 1/1 ns output timing measurement reference level 1.4 v output load condition see fig. 2 dc output load circuit ac output load circuit 3.3v 1200? 870? output 50pf v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma vtt = 1.4v 50? output 50pf z0 = 50?
WV3DG7266V-D1 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 1 preliminary operating ac parameters parameter symbol 77510 unit note min max min max min max clk cycle time cas latency=3 t cc 7.5 1000 7.5 1000 10 1000 ns 1 cas latency=2 7.5 10 10 clk to valid output delay cas latency=3 t sac 5.4 5.4 6 ns 1, 2 cas latency=2 5.4 6 6 output data hold time cas latency=3 t oh 333 ns 2 cas latency=2 3 3 3 clk high pulse width t ch 2.5 2.5 3 ns 3 clk low pulse width t cl 2.5 2.5 3 ns 3 input setup time t ss 1.5 1.5 2 ns 3 input hold time t sh 0.8 0.8 1 ns 3 clk to output in low-z t slz 111ns2 clk to outpu in hi-z cas latency=3 t shz 5.4 5.4 6 ns cas latency=2 5.4 6 6 notes : 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
WV3DG7266V-D1 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 1 preliminary ordering information speed cas latency height* wv3dg7266v10d1 100mhz cl=2 31.75 (1.250) wv3dg7266v7d1 133mhz cl=2 31.75 (1.250) wv3dg7266v75d1 133mhz cl=3 31.75 (1.250) notes: ? consult factory for availability of lead-free products. (f = lead-free, g = rohs compliant) ? vendor speci? c part numbers are used to provide memory components source control. the place holder for this is shown as lower case x in the part numbers above and is to be replaced with the respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consult factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option package dimensions for d1 67.56 (2.66) 63.60 (2.50) 4.60 (0.18) 23.20 (0.91) 32.80 (1.29) 3.30 (0.13) 2 - 1.80 (0.07) 2 - r 2.00 (0.078) min 1.00 0.10 (0.04 0.0039) 31.75 (1.25) 3.20 (0.125) min 4.00 (0.157) min 20.00 (0.79) 4.00 0.10 (0.16 0.039) 6.00 (0.24) 2.10 (0.083) 2.50 (0.10) 3.80 (0.15) 15961 143 2 144 6.35 (0.250) max package dimensions for d1 * all dimensions are in millimeters and (inches).
WV3DG7266V-D1 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2005 rev. 1 preliminary document title 512mb C 2x32mx72 sdram unbuffered, w/pll revision history rev # history release date status rev 0 created 4-05 preliminary rev 1 1.1 update functional block diagram 8-05 preliminary
|
